Refactor: bind the DFX collectors' per-run output separately - #2093

Summary

Each DFX collector's initialize() / init() took two unrelated kinds of
argument: the device resources to allocate, and the current run's artifact
configuration. Those have different lifetimes — resources belong to the device,
configuration to a run — and conflating them is part of what forces the
collectors to be torn down and rebuilt every run (#2078).

The configuration now has its own binder, set_run_output(), on the three
collectors that have one:

Callers bind it before initialize(), which is where the runners already sat:
apply_call_config() runs inside simpler_prepare_run, ahead of
prepare_execution. dep_gen and scope_stats have no per-run arguments and
are untouched.

initialize() still runs once per run, so the level still reaches the device
header from the member the setter wrote. No behaviour changes.

The sizing arguments deliberately stay

An earlier revision of this PR also moved num_aicore / aicpu_thread_num to
the platform maxima, on the reasoning that a collector outliving a run cannot be
sized to that run. CI caught that, and the reason is worth recording:

num_aicore is not a capacity number — it is the addressing basis for the
shared-memory layout. Only the first pool array starts at a fixed offset;
every one after it is derived from num_aicore:

get_aicore_buffer_states(base, num_cores)      = base + calc_perf_data_size(num_cores)
get_sched_phase_buffer_states(base, num_cores) = base + calc_perf_data_size(num_cores)
                                                      + num_cores * sizeof(AicoreTaskPool)

The AICPU side computes those same offsets from its own worker count
(chip_swimlane_collector_aicpu.cpp:333, :822). Widening only the host's basis
desynchronizes two views of one region: each side then reads and writes different
addresses in it. The symptom is silent — no error anywhere, just

PERF        count mismatch (collected=5 + dropped=0 != device_total=34, silent_loss=29)
SCHED_PHASE count mismatch (collected=2 + dropped=0 != device_total=0,  silent_loss=-2)

A negative silent_loss is the giveaway: records cannot be lost below zero,
so the two sides must be addressing different memory.

Making the layout independent of a run requires changing both sides in one
commit, and belongs with the residency work rather than here.

Testing

• All four variants build (a2a3/a5 × onboard/sim)
• cpput 128/128 — the collector tests call these signatures directly and
  were updated
• a5sim full sweep: host_build_graph 18 passed, tensormap_and_ringbuffer
  46 passed
• DFX lanes on both arches, which is what the plain sweep misses because
  it passes no diagnostic flags: a5 chip_swimlane 4 passed; a2a3 dfx 3 + 9
  passed — all with --enable-chip-swimlane --enable-dep-gen
• clang-format, cpplint, check-headers, check-english-only,
  check-retired-names, check-kernel-wire-isolation
• Everything above re-run after rebasing onto Refactor: confine host_build_graph orchestration to the host #2094, which touches
  dep_gen_host_graph.h and the hbg orchestration API
• No onboard run locally — this box is a2a3 silicon; covered by CI

Step 2 of the plan in
#2078 (comment),
following #2091.